1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a multi-bit testing function.
2. Description of the Background Art
In a semiconductor memory device wafer test, a multi-bit test is performed so as to increase the number of wafers which can be tested by one tester. In this multi-bit test, a plurality of bits are degenerated to thereby decrease the number of input/output terminals employed in the test. In case of a semiconductor memory device which functions as a word organization of xe2x80x9cxc3x9716xe2x80x9d, for example, four bits are degenerated to one bit by using a multi-bit test and a test data write/read test is performed to four input/output terminals, whereby a test can be performed to all memory cells.
The numbers of drivers and comparator pins to be provided in a tester employed for a test are determined according to the specification of the tester. Therefore, if the number of input/output terminals necessary to measure one device using a multi-bit test decreases, it is possible to increase the number of devices which can be simultaneously measured and to thereby enhance testing efficiency.
FIG. 24 is a functional block diagram for functionally describing data-read-related sections of a conventional semiconductor memory device which has a multi-bit testing function. It is noted that FIG. 24 typically shows only important sections related to data output in the semiconductor memory device.
Referring to FIG. 24, the semiconductor memory device includes a memory cell array MA100 which stores data, sense amplifiers SA100 to SA103 which detect data read from memory cell array MA100 to bit line pairs BL100 to BL103, input/output control circuits 711 to 714 which amplify the data read from sense amplifiers SA100 to SA103 to I/O line pairs LIO100 to LIO103, respectively, and switches S101 to S104 which selectively output the data received from input/output control circuits 711 to 714 in accordance with a multi-bit test mode signal TMBT whose logic level becomes H (logic high)-level in a multi-bit test mode, to data bus pairs NDB0 to NDB3 or TDB0 to TDB3, respectively.
Input/output control circuits 711 to 714 include preamplifiers/read data bus drivers which amplify the data read to I/O line pairs LIO100 to LIO103 and which output the amplified data to switches S101 to S104 during data read, respectively, and write amplifiers/write buffers which output the data received from switches S101 to S104 to I/O line pairs LIO100 to LIO103 during data write, respectively. In addition, sense amplifiers SA100 to SA103 write the write data received from the write amplifiers/write buffers of input/output control circuits 711 to 714 through I/O line pairs LIO100 to LIO103, to bit line pairs BL100 to BL103, respectively.
The semiconductor memory device also includes data bus pairs NDB0 to NDB3 which are connected to input/output control circuits 711 to 714 through switches S101 to S104 in a normal operation other than the multi-bit test mode (which normal operation will be referred to as xe2x80x9cnormal operation modexe2x80x9d opposed to the multi-bit test mode, hereinafter), and data bus pairs TDB0 to TDB3 which are connected to input/output control circuits 711 to 714 through switches S101 to S104 in the multi-bit test mode, respectively. Data bus pairs NDB0 to NDB3 are formed of data buses NDB0 and /NDB0, data buses NDB1 and /NDB1, data buses NDB2 and /NDB2 and data buses NDB3 and /NDB3 which transmit complementary data, respectively. Data bus pairs TDB0 to TDB3 is formed of data buses TDB0 and /TDB0, data buses TDB1 and /TDB1, TDB2 and /TDB2 and TDB3 and /TDB3 which transmit complementary data, respectively.
The semiconductor memory device further includes an I/O combiner 741 which degenerates and outputs the read data of four bits received from data bus pairs TDB0 to TDB3, a data bus pair RTDB which transmit the data degenerated by the I/O combiner 741, a read amplifier 721 which receives the data from data bus pair NDB0 and that from RTDB, selects one of the data in accordance with multi-bit test mode signal TMBT, amplifies the signal level of the selected data and outputs the data to a data bus pair RDAMP0, read amplifiers 722 to 724 which receives the data from data bus pairs NDB1 to NDB3, amplifies the signal levels of the data and outputs the data to data bus pairs RDAMP1 to RDAMP3, respectively, and output circuits 731 to 734 which receive the data outputted from read amplifiers 721 to 724 and output the data to the outside of the semiconductor memory device, respectively. Data bus pair RTDB is formed of data buses RTDB and /RTDB which transmit complementary data.
In a multi-bit test for this semiconductor memory device, before reading data from memory cell array MA100, data at the same logic level are written to the corresponding memory cells of memory cell array MA100. In a multi-bit test mode, the logic level of multi-bit test mode signal TMBT becomes H level and switches S101 to S104 connect input/output control circuits 711 to 714 to data bus pairs TDB0 to TDB3, respectively.
I/O combiner 741 degenerates the data of four bits received from data bus pairs TDB0 to TDB3. Namely, if the data of four bits received from data bus pairs TDB0 to TDB3 are all at the same logic level, it is determined that data write and read have been normally performed and H-level data and L (logic low)-level data are outputted to data bus pair RTDB and /RTDB, respectively. If the data of four bits are not at the same logic level, it is determined that data write and read have not been normally performed and H-level data is outputted to each of data bus pair RTDB and /RTDB.
In the multi-bit test mode, only read amplifier 721 is activated among read amplifiers 721 to 724. If the data received from data bus pair RTDB and /RTDB are at H level and L level, respectively, read amplifier 721 determines that data write and read have been normally performed and outputs an H-level signal to output circuit 731. If the data received from data bus pair RTDB and /RTDB are both at H level, read amplifier 721 determines that data write and read have not been normally performed and outputs an L-level signal to output circuit 731. Output circuit 731 outputs the received data to the outside of the semiconductor memory device. Other signals CKD, RDAI, /RDAI, RDAE and /RDAE received by read amplifiers 721 to 724 will be described later.
On the other hand, in a normal operation mode, the logic level of multi-bit test mode signal TMBT becomes L level and switches S101 to S104 connect input/output control circuits 711 to 714 to data bus pairs NDB0 to NDB3, respectively. Read amplifiers 721 to 724 amplify the data read from memory cell array MA100 to data bus pairs NDB0 to NDB3 and output the amplified data to output circuits 731 to 734, respectively.
FIGS. 25 and 26 are circuit diagrams for describing the circuit configuration of read amplifier 721. Referring to FIG. 25, read amplifier 721 includes an N-channel MOS transistor N101 which is connected to data bus NDB0 and a node RD and which has a gate receiving a signal /RDAI, an N-channel MOS transistor N102 which is connected to data bus /NDB0 and a node /RD and which has a gate receiving signal /RDAI, an N-channel MOS transistor N103 which is connected to node RD and data bus RDAMP and which has a gate receiving signal /RDAE, and an N-channel MOS transistor N104 which is connected to node /RD and data bus /RDAMP and which has a gate receiving signal /RDAE.
If signal /RDAI is at H level, N-channel MOS transistors N101 and N102 operate as an input circuit which takes in data on data bus pair NDB0 and /NDB0 into node pair RD and /RD. If signal /RDAE is at H level, N-channel MOS transistors N103 and N104 operate as an input circuit which takes in data on node pair RD and /RD into data bus pair RDAMP0 and /RDAMP0.
Read amplifier 721 also includes an N-channel MOS transistor N105 which is connected to data bus RDAMP0 and a ground node GND and which has a gate receiving signal CKD, and an N-channel MOS transistor N106 which is connected to data bus /RDAMP0 and ground node GND and which has a gate receiving signal CKD.
If signal CKD is at H level, N-channel MOS transistors N105 and N106 operate as an equalization circuit which equalizes data bus pair RDAMP and /RDAMP0 to L level.
Read amplifier 721 further includes an N-channel MOS transistor N107 which is connected to data bus RDAMP0 and a node ND102 and which has a gate connected to data bus /RDAMP0, an N-channel MOS transistor N108 which is connected to node ND102 and data bus /RDAMP0 and which has a gate connected to data bus RDAMP0, a P-channel MOS transistor P101 which is connected to data bus RDAMP0 and a node ND101 and which has a gate connected to data bus /RDAMP0, a P-channel MOS transistor P102 which is connected to node ND101 and data bus /RDAMP0 and which has a gate connected to data bus RDAMP0, a P-channel MOS transistor P103 which is connected to a power supply node Vcc and node ND101 and which has a gate receiving signal /RDAE, and an N-channel MOS transistor N109 which is connected to node ND102 and a ground node GND and which has a gate receiving signal RDAE.
If signal RDAE is at H level, N-channel MOS transistors N107 to N109 and P-channel MOS transistors P101 to P103 operate as a differential amplifier which amplifies a low amplitude signal, which is taken in from data bus pair NDB0 and /NDB0 into data bus pair RDAMP0 and /RDAMP0, to a full amplitude signal ranging from a power supply voltage level to a ground level.
Referring to FIG. 26, read amplifier 721 also includes a NAND gate 751 which receives the signal on data bus RTDB and multi-bit test mode signal TMBT, a NAND gate 752 which receives the signal on data bus /RTDB and multi-bit test mode signal TMBT, a NOR gate 753 which receives the outputs of NAND gates 751 and 752, an inverter 754 which inverts the output of NOR gate 753, an N-channel MOS transistor N110 which is connected to the output node of inverter 754 and node RD and which has a gate receiving a signal /MBI, and an N-channel MOS transistor N111 which is connected to the output node of NOR gate 753 and node /RD and which has a gate receiving signal /MBI.
NAND gates 751 and 752 are activated if multi-bit test mode signal TMBT is at H level. N-channel MOS transistors N110 and N111 operate as an input circuit which takes in the outputs of NAND gates 753 and inverter 754 into node pair RD and /RD, respectively.
Signal RDAE is a signal which activates the read amplifier during data read. Signal RDAI is a signal which logic level becomes H level if the semiconductor memory device turns into a data readable state in the multi-bit test mode. Signal CKD is a signal which equalizes data bus pair RDAMP0 and /RDAMP0 to L level before data is read to data bus pair RDAMP0 and /RDAMP0. Signal /MBI is a signal which logic level becomes H level after I/O combiner 741 outputs data to data bus pair RTDB and /RTDB.
In read amplifier 721, the logic level of signal CKD becomes H level before data is read and data bus pair RDAMP and /RDAMP0 are equalized to L level. And, in the normal operation mode, the logic levels of signals RDAE and RDAI become L level when data is read and data at low amplitude signal level is read from data bus pair NDB0 and /NDB0 to data bus pair RDAMP0 and /RDAMP0. Thereafter, the logic level of signal RDAE becomes H level and signals on data bus pair RDAMP0 and /RDAMP0 are amplified to full amplitude by a differential amplifier constituted by N-channel MOS transistors N107 to N109 and P-channel MOS transistors P101 to P103.
Meanwhile, in a multi-bit test mode, the logic level of multi-bit test mode signal TMBT becomes H level, and if the data received from data bus pair RTDB and /RTDB are at H level and L level, respectively, i.e., the logic levels of data of four bits read in parallel from memory cell array MA100 coincide with one another, then an L-level signal is outputted to the output node of NOR gate 753 and the logic level of the output of inverter 754 becomes H level. On the other hand, if the data received from data bus pair RTDB and /RTDB are both at H level, i.e., the logic levels of data of four bits read in parallel from memory cell array MA100 do not coincide, then an H-level signal is outputted to the output node of NOR gate 753 and the logic level of the output of inverter 754 becomes L level.
The logic levels of signals /MBI, /RDAI and /RDAE become H level, L level and H level, respectively, N-channel MOS transistors N110, N111, N103 and N104 are turned on, N-channel MOS transistors N101 and N102 are turned off, and data is read from data bus pair TDB and /TDB to data bus pair RDAMP0 and /RDAMP0. Thereafter, the logic level of signal RDAE becomes H level and the signals on data bus pair RDAMP0 and RDAMP0 are amplified to full amplitude by a differential amplifier constituted by N-channel MOS transistors N107 to N109 and P-channel MOS transistors P101 to P103.
Each of read amplifiers 722 to 724 are formed of the same constituent elements as those of read amplifier 721 except that NAND gates 751 and 752, NOR gate 753, inverter 754 and N-channel MOS transistors N110 and N111 are not provided. Since the other constituent elements of each of read amplifiers 722 to 724 are the same as those of read amplifier 721, they will not be repeatedly described.
FIG. 27 is a functional block diagram for functionally describing data-write-related sections of a conventional semiconductor memory device having a multi-bit testing function. It is noted that FIG. 27 typically shows only the important sections related to data input in the semiconductor memory device.
Referring to FIG. 27, the semiconductor memory device includes input circuits 771 to 774 which input write data from the outside of the semiconductor memory device, a write data bus driver 761 which receives the write data outputted from input circuit 771 and which selectively outputs the data to data bus pair NDB0 or WTDB in accordance with multi-bit test mode signal TMBT, a data bus pair WTDB which transmit the write data outputted from write data bus driver 761 to data bus pairs TDB0 to TDB3, and write data bus drivers 762 to 764 which receive the write data outputted from input circuits 772 to 774 and which output the write data to data bus pairs NDB1 to NDB3, respectively. Data bus pair WTDB is formed of data buses WTDB and /WTDB which transmit complementary data. Data bus WTDB is branched to data buses TDB0 to TDB3 and data bus /WTDB is branched to data buses /TDB0 to /TDB3.
Since the other circuit configuration is already described with reference to FIG. 24, it will not be repeatedly described herein.
In a multi-bit test mode, the write data is inputted only to input circuit 771. Write data bus driver 761 outputs the write data received from input circuit 771 to data bus pair WTDB in accordance with multi-bit test mode signal TMBT and the data outputted to data bus pair WTDB is transmitted to data bus pairs TDB0 to TDB3 which are branched from data bus pair WTDB.
Switches S101 to S104 connect data bus pairs TDB0 to TDB3 to input/output control circuits 711 to 714 in accordance with multi-bit test mode signal TMBT. The data at the same logic level are written from data bus pairs TDB0 to TDB3 to the memory cells of memory cell array MA100 through input/output control circuits 711 to 714 and sense amplifiers SA100 to SA103, respectively.
In a normal operation mode, write data bus drivers 761 to 764 receive the write data, which are inputted to input circuits 771 to 774, from input circuits 771 to 774 and output the write data to data bus pairs NDB0 to NDB3, respectively. Switches S101 to S104 connect data bus pairs NDB0 to NDB3 to input/output control circuits 711 to 714 in accordance with multi-bit test mode signal TMBT and data are written from data bus pairs NDB0 to NDB3 to the memory cells of memory cell array MA100 through input/output control circuits 711 to 714 and sense amplifiers SA100 to SA103, respectively.
According to the conventional semiconductor memory device, in the multi-bit test, test data at the same logic level are written in parallel to a plurality of bits and H-level data is outputted if the logic levels of the respective data read in parallel from the plurality of bits coincide and it is determined that these bits are normal. However, even if all the respective data are erroneously read, the logic levels of the respective data are consistent and H-level data is, therefore, outputted, as well. That is, the conventional semiconductor memory device cannot detect a word line defect (which is also referred to as an X line defect) from which all the data in the same row are erroneously read in the multi-bit test. For that reason, a test for separately detecting an X line defect in the normal operation mode other than the multi-bit test is performed in the conventional semiconductor memory device, with the result that test time disadvantageously increases.
Further, to solve the above-described problem, there is proposed inverting the logic levels of a part of data of a plurality of bits and writing the level-inverted data to the memory cell array. In this case, it is necessary to externally set, as a test mode, the logic levels of which data bits are to be inverted. If there are many terminals employed for the setting, the number of devices which can be simultaneously measured in a multi-bit test disadvantageously decreases and the testing efficiency of the multi-bit test eventually deteriorates.
The present invention is made to solve the above-mentioned problems. It is an object of the present invention to provide a semiconductor memory device which can perform a multi-bit test capable of detecting an X line defect.
It is another object of the present invention to provide a semiconductor memory device which can minimize the number of terminals employed for the setting of a test mode if a multi-bit test capable of detecting an X line defect is performed and which can maintain the testing efficiency of the multi-bit test.
According to the present invention, a semiconductor memory device includes: a memory cell array storing data; a determination circuit receiving expected value data for logic levels of read data of a plurality of bits read in parallel from the memory cell array, and determining whether the logic levels of the read data coincide with a logic level of the expected value data in a multi-bit test; and an output circuit outputting a determination result of the determination circuit.
It is preferable that the determination circuit determines whether a logic level of degenerated data obtained by degenerating the read data of the plurality of bits coincides with the logic level of the expected value data.
It is preferable that the semiconductor memory device further includes: an input circuit receiving degenerated data obtained by degenerating write data of a plurality of bits written in parallel to the memory cell array; a test mode control circuit generating a write data pattern signal for the write data of the plurality of bits on the basis of an internal test pattern setting signal generated internally; a write data inversion circuit inverting logic level of a part of the write data of the plurality of bits written in parallel to the memory cell array on the basis of the write data pattern signal in the multi-bit test; and a read data inversion circuit re-inverting the logic level of the data the logic level of which is inverted by the write data inversion circuit for the read data of the plurality of bits read in parallel from the memory cell array, and outputting the re-inverted read data of the plurality of bits to the determination circuit.
As described above, according to the semiconductor memory device of the present invention, the determination circuit determines whether the logic levels of data of a plurality of bits read in parallel from the memory cell array coincide with that of the expected value data in the multi-bit test. Therefore, even if all the read data are erroneously read such as an X line defect, it is possible to discriminate the defect.
Further, according to the semiconductor memory device of the present invention, the write data inversion circuit can invert the logic level of a part of data of a plurality of bits written in parallel to the memory cell array on the basis of the internal test pattern setting signal which is internally generated. Therefore, it is possible to enhance defect detection capability, to prevent the number of test target devices simultaneously measured in the test from decreasing, and to enhance testing efficiency as a whole.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.